The present invention relates generally to memory circuits utilizing inversion controlled switches; more particularly, the present invention is directed to a novel inversion controlled switch memory array providing superior device-to-device isolation.
The inversion controlled switch is described in U.S. Pat. No. 3,979,613 to Harry Kroger and assigned to Sperry Rand Corporation. A three terminal inversion controlled switch is described therein in which the emitter-collector impedance exhibits bistable states achieved and maintained through the control of emitter-collector voltage with or without control of the base current.
It has been proposed to construct a memory array of inversion controlled switches arranged in rows and columns whereby a controllable voltage may be applied to individual columns of switches at their collector electrodes while a controllable current is applied to individual rows of switches through their base terminals. By coupling the base terminals of each row of switches to a common current source, it is difficult to prevent current from flowing between devices, such that the threshold voltage levels of switches within each row may be uncontrollably and adversely affected. Under certain operating conditions, it is possible for a device in a high impedance or OFF state to be incorrectly switched to a low impedance or ON state by sinking current from another switch in the row that is ON.